A conventional tristate output buffer circuit is illustrated in FIGS. 1 & 2. FIG. 1 provides a logic diagram summary of the circuit implementation of FIG. 2. A basic inverting TTL output buffer circuit B2 when operating in the bistate mode, transmits binary data signals of high and low potential levels from the input V.sub.IN to the output V.sub.OUT. Output buffer circuit B2 incorporates the conventional pullup Darlington transistor element pair Q4, Q5 for sourcing current from the high potential rail V.sub.CC to the output V.sub.OUT. Pulldown transistor element Q3 sinks current from the output V.sub.OUT to the low potential rail GND. Phase splitter transistor element Q2 controls the conducting states of the pullup transistor element Q4, Q5 and pulldown transistor element Q3 in opposite phase in response to data signals from input transistor element Q1 which is in turn coupled to the input V.sub.IN through diode element D3. Resistors R1, R2 and R3 provide respective current sources from the high potential rail V.sub.CC for the switching transistor elements. During operation in the bistate mode, input data signals at high and low potential levels are inverted, amplified, and transmitted to the output V.sub.OUT as output data signals at low and high potential levels.
For establishing a high impedance third state Z at the output V.sub.OUT, a tristate output enable circuit is also provided. The tristate mode is used for operation of the TTL output buffer circuit on a common bus with multiple output circuits. When one of the output buffer circuits is operating in the bistate mode, transmitting binary data signals on the common bus, the other output buffer circuits are "tristated" and present a high impedance at the respective outputs V.sub.OUT coupled to the common bus. The tristate mode avoids interference when other output circuits are using the common bus.
The tristate output enable circuit includes an inverting OE buffer circuit B1 with an OE signal input for receiving OE signals of high and low potential level. The OE signals are inverted by the OE buffer circuit B1 providing OE signals at the OE signal output of the OE buffer B1. An OE signal output circuit from the OE buffer B1 is provided by diodes D1 and D2 which couple the OE signals to the pullup transistor element Q4, Q5 and the phase splitter transistor element Q2 respectively. In particular diode D1 provides a one way path from the base of transistor Q4 to the output OE circuit B1 while diode D2 provides a one way path from the base of transistor Q2 to the OE buffer B1.
With an OE high potential level signal (derived from an OE low potential level signal) is applied at the OE signal output circuit, the paths through diodes D1 and D2 are blocked and the TTL output buffer circuit B2 operates in the normal bistate mode, transmitting binary signals from the input V.sub.IN to the output V.sub.OUT. With a low potential level OE signal (derived from a high potential level OE signal) is applied at the OE signal output circuit, diodes D1 and D2 provide discharge paths which discharge the bases of the pullup transistor element Q4 and phase splitter transistor element Q2, respectively. With all of the output switching transistors turned off and held off, the output V.sub.OUT presents a high impedance at the common bus.
Causing transition from a binary data signal high potential level H or low potential level L at the output V.sub.OUT to the high Z state is referred to herein as tristating or disabling the output buffer circuit. The signal propagation times or transition times for disabling the output buffer circuit are also referred to herein as the disable times tpHZ and tpLZ. Causing transition from the tristate mode back to the bistate mode of operation is referred to herein as enabling the output buffer circuit. The signal propagation times or signal transition times for enabling the output buffer circuits are also referred to herein as enable times tpZH and tpZL.
A disadvantage of the conventional prior art TTL tristate output devices coupled to a common bus is that there may be considerable variation in the binary data signal high and low potential levels with consequent variation and overlap in the enable and disable times for the respective output devices. Furthermore tristate output devices from different logic families with different logic signal potential levels may be coupled to a common bus with further variation and overlap in enable and disable times. Overlap of operation of active output devices on the common bus occurs when the current output device is enabled while a previous output device is not yet disabled. The resulting interference of active output devices on a common bus is known as the "bus contention problem" and may result in false data signals etc.
The tristate output buffer circuit of FIGS. 1 and 2 may incorporate additional circuit features. For example the output buffer circuit B2 may include an AC Miller killer circuit for operation in the bistate mode. The AC Miller killer circuit prevents turn on of the pulldown transistor element Q3 during binary data signal transition from low to high potential level at the output V.sub.OUT by discharging any Miller current generated from the collector to base nodes through the internal Schottky diode of pulldown Schottky transistor element Q3. Such an AC Miller killer circuit is described for example in the Robert W. Bechdolt U.S. Pat. No. 4,321,490.
Additionally the output buffer circuit B2 may incorporate a DC Miller killer circuit for operation in the tristate mode. The DC Miller killer circuit similarly discharges the base of the pulldown transistor element Q3 to prevent unintended turn on of the pulldown transistor element Q3 by parasitic Miller current. The DC Miller killer circuit operates during the tristate mode in response to processed OE signals. Such DC Miller killer circuits are described for example in the David A. Ferris U.S. Pat. No. 4,311,927 the Ferris et al. U.S. Pat. No. 4,581,550, the Farhad Vazehgoo U.S. Pat. No. 4,649,297 etc.